On Complexity Reduction of FIR Digital Filters Using Constrained Least Squares Solution

| In this paper, we apply constrained least squares solution (CLS) to the problem of reducing the number of operations in FIR digital lters with a motivation of reducing its power consumption. The constraints are deened by the maximum allowable add/subtract operations in forming the products which are used in computing the output. We show that truncation and rounding of coeecients can be viewed as power constrained least squares (PCLS) solutions. Further, we show that in dedicated DSP processor based architectures it is possible to reduce power by using PCLS coeecients along with appropriately modiied multipliers. It is also shown that Booth multiplier eeectively reduces the complexity of such lters, thereby increasing power savings. Finally, we show that typically 30% to 45% reduction in number of operations can be obtained for systems employing uncoded and Booth recoded multipliers, respectively.